Comprehensive model-based error analysis of multiple concurrent, time-interleaved, and hybrid ultra-wideband analogue-to-digital conversion

In this paper, a comprehensive parametric error model of ultra-wideband analogueto-digital conversion (ADC) is developed, which can likewise be applied for single ultra-fast ADC, multiple concurrent ADC (MC-ADC), time-interleaved ADC (TIADC) and hybrid ADC (H-ADC) as a combination of TIand MC-ADC. The error model comprises quantisation, overflow saturation, DC-offset, gain error, time delay, and time jitter due to sample-and-hold (S&H) circuit(s) and clock generator(s). The impact of all of these system parameters on ADC performance is analysed by analytic evaluation of the error model assuming an arbitrary FDM input spectrum. By using either explicitly given deterministic and stochastic parameters, respectively, assuming normally distributed deviations from the nominal values, we derive closed-form equations for the signal-to-noise and distortion ratio (SNDR) at the analogue-to-digital interface (ADI) output port. The features and performance of the different ADC approaches are investigated and compared with each other by a challenging future application of satellite onboard processing [13]: 1 GHz overall FDM bandwidth with 12 MHz channel spacing.